1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priorities are claimed on Japanese Patent Applications Nos. 2010-266916, filed Nov. 30, 2010 and 2011-105376, filed May 10, 2011, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In recent years, semiconductor devices such as DRAMs (Dynamic Random Access Memories) have been miniaturized. Accordingly, if a gate length of a transistor is shortened, a short channel effect of the transistor is noticeable. As a result, sub-threshold current increases and a threshold voltage (Vt) of the transistor decreases.
Further, when impurity concentration of a semiconductor substrate increases in order to suppress the decrease of the threshold voltage (Vt) of the transistor, junction leak current increases.
Thereby, when a memory cell of a semiconductor device such as a DRAM is miniaturized, degradation of a refresh characteristic is a severe problem.
As a structure for resolving such problems, a trench gate transistor in which a gate electrode is buried in a trench formed in a main surface of a semiconductor substrate (also called “recess channel transistor”) is disclosed in Japanese Patent Laid-open Publication No. 2006-339476 and Japanese Patent Laid-open Publication No. 2007-081095.
As the transistor is a trench gate transistor, an effective channel length (gate length) can be secured physically sufficiently and a DRAM including a fine cell having a minimum processing dimension equal to or less than 60 nm can be realized.
Further, a DRAM including two trenches formed to be adjacent to each other in a semiconductor substrate, gate electrodes formed in the respective trenches through a gate insulating film, a first impurity diffusion region formed in a main surface of the semiconductor substrate located between the two gate electrodes and common to the two gate electrodes, and a second impurity diffusion region formed in the main surface of the semiconductor substrate located at a side of an element isolation region of the two gate electrodes is disclosed in Japanese Patent Laid-open Publication No. 2007-081095.